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mic4100/1 100v half bridge mosfet drivers micrel inc. ? 2180 fortu ne drive ? san jose, ca 95131 ? usa ? te l +1 (408) 9 44-08 00 ? fax + 1 (408) 474-1000 ? htt p :/ /www.micre l.com march 20 06 m999 9-03 150 6 general description the mi c41 0 0 /1 a r e high freq uen cy, 100v half b r idge mosfet d r i v er ics fe atu r ing fa st 30n s p r op agatio n del ay times. the low-sid e an d high -si d e gate drive r s are indep ende ntly controlled and match ed to withi n 3n s typical. th e mic410 0 h a s cm os inp u t threshold s , a nd th e mic410 1 ha s ttl inp u t threshold s . the mic4 100/1 inclu de a hig h voltage inte rnal diode tha t cha r ge s the high- side g a te driv e bootst rap capa citor. a robu st, hig h -spee d, and low po we r le vel shifter p r o v ides clea n level transitio ns to the high si de output. the robu st operation of the mic41 0 0 / 1 ensu r e s t he output s a r e not affected by supply glitche s , hs ringin g belo w g r ou n d , or hs sle w in g with high sp eed voltage transitio ns. under- voltage prote c tion is p r ovi ded on b o th the low-sid e and high-sid e driv ers. the mic4 10 0 is available in the soic-8l pa ckage with a junctio n ope rating ran ge from ?40 c to + 1 25 c. data sheet s and suppo rt doc umentatio n can be fou nd o n micrel?s web site at www. micrel.com. fe ature s ? bootstra p su pply max voltage to 118v dc ? supply voltag e up to 16v ? drive s hig h - and lo w-sid e n-ch ann el mosfets with indep end ent inputs ? c m os input thres h olds (mi c 4100) ? ttl input thresh old s (MIC4101 ) ? on-chi p boot stra p diod e ? fast 30 ns p r o pagatio n time s ? drive s 10 00p f load with 1 0ns rise and f a ll times ? low p o wer consumptio n ? supply und er-voltage p r ote c tion ? 3 ? pull up , 3 ? pull down o u tput re sista n c e ? space savin g soic-8l p a ckag e ? ?40 c to + 125 c ju nctio n tempe r atu r e range applicati o ns ? high voltag e buck conve r ters ? push -pull con v ert e r s ? full- an d half-brid ge converters ? active clamp forward conv erters _ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ ___ _ __ ___ _ __ ___ ___ ___ ___ _ ty pical a pplic ation hi mic4100 so-8 pwm controller li ho hs lo hb vdd 9v to 16v bias 100v supply gnd v out 100v bu c k re g u l ato r solu tio n
mic r el, inc . mic41 00/1 march 20 06 2 m9999-0315 06 ordering inform ation part nu mb er s t a n d a r d p b - f r e e i n p u t junc tion temp. range package mic410 0bm mic410 0ym cmo s ?40 to + 125 c so ic-8l mic410 1bm mic410 1ym t t l ?40 to + 125 c so ic-8l pin c onfi gur ation 1 vdd hb ho hs 8l o vss li hi 7 6 5 2 3 4 soic-8l (m) pin d e s c r i ption pin numbe r pin na me pin f unc tio n 1 v d d positive supply to lo w e r gate drivers. dec ouple this pin to vss (pin 7). bootstrap diod e con necte d to hb (pin 2). 2 h b high-s i de b oot strap supp l y . e x tern al b ootstrap cap a citor is requir ed. co nn ect positive si de of bootstrap cap a citor to th is pi n. bootstrap di ode is o n -chi p. 3 ho high-s i de o u t put. conn ect to gate of high-s i de p o w e r mo sf et . 4 h s high-s i de s our ce conn ection. conn ect to sou r ce of high-si d e po w e r mo sf et . conn ect neg ati v e side of bo ot strap capac itor to this pin. 5 h i high-s i d e i n p u t . 6 l i lo w - si d e i nput . 7 vss chip n e g a tive supply , g ener ally w i ll b e grou n d . 8 lo lo w - si de o u tp ut. connect to gate of lo w - s i de po w e r mo sf et .
micrel, inc. mic4100/1 march 2006 3 m9999-031506 absolute maximum ratings (1) supply voltage (v dd , v hb ? v hs ) ...................... -0.3v to 18v input voltages (v li, v hi ) ......................... -0.3v to v dd + 0.3v voltage on lo (v lo ) .............................. -0.3v to v dd + 0.3v voltage on ho (v ho ) ......................v hs - 0.3v to v hb + 0.3v voltage on hs (contin uous) .............................. -1v to 110v voltage on hb ..............................................................118v average current in vdd to hb diode.......................100ma junction temperature (t j ) ........................?55c to +150c storage temperature (t s ) ..........................-60c to +150c eds rating (3) ..............................................................note 3 operating ratings (2) supply voltage (v dd )........................................ +9v to +16v voltage on hs ................................................... -1v to 100v voltage on hs (repetitive transient) .................. -5v to 105v hs slew rate............................................................ 50v/ns voltage on hb ...................................v hs + 8v to v hs + 16v and............................................ v dd - 1v to v dd + 100v junction temperature (t j ) ........................ ?40c to +125c junction thermal resistance soic-8l ( ja )...................................................140 c/w electrical characteristics (4) v dd = v hb = 12v; v ss = v hs = 0v; no load on lo or ho; t a = 25c; unless noted. bold values indicate ?40c < t j < +125c. parameter symbol condition min typ max units supply current v dd quiescent current i dd li = hi = 0v 40 150 200 a v dd operating current i ddo f = 500khz 2.5 3.4 ma total hb quiescent current i hb li = hi = 0v 25 150 200 a total hb operating current i hbo f = 500khz 1.4 2.5 3 ma hb to v ss current, quiescent i hbs v hs = v hb = 110v 0.05 1 a hb to v ss current, operating i hbso f = 500khz 10 a input pins: mic4100 (cmos input ) low level input voltage threshold v il 4 3 5.3 v high level input voltage threshold v ih 5.7 7 8 v input voltage hysteresis v ihys 0.4 v input pulldown resistance r i 100 200 500 k ? input pins: MIC4101 (ttl) low level input voltage threshold v il 0.8 1.5 v high level input voltage threshold v ih 1.5 2.2 v input pulldown resistance r i 100 200 500 k ?
mic r el, inc . mic41 00/1 pa r a me ter s y m b o l conditi o n m i n ty p ma x units un d er vo ltag e pro t ectio n v dd risin g t h reshol d v ddr 6.5 7.4 8.0 v v dd t h reshold h y ster esis v ddh 0 . 5 v hb risin g t h reshold v hb r 6.0 7.0 8.0 v hb t h reshold h y ster esis v hb h 0 . 4 v boots t r a p diode lo w - c u rrent f o r w ard v o ltag e v dl i v dd-hb = 100 a 0 . 4 0 . 5 5 0.70 v high- curre nt f o r w ard v o ltag e v dh i v dd-hb = 100ma 0 . 7 0 . 8 1.0 v d y namic r e sis t ance r d i v dd-hb = 100ma 1 . 0 1 . 5 2.0 ? lo ga te dr i v er lo w l e vel o u t put voltag e v oll i lo = 100ma 0 . 2 2 0 . 3 0.4 v high l e ve l o u tput voltag e v ohl i lo = -100ma, v ohl = v dd - v lo 0 . 2 5 0 . 3 0.45 v peak sink c u rr ent i ohl v lo = 0v 2 a peak sourc e c u rrent i oll v lo = 12v 2 a ho gate dri v e r lo w l e vel o u t put voltag e v olh i ho = 100ma 0 . 2 2 0 . 3 0.4 v high l e ve l o u tput voltag e v ohh i ho = -100ma, v ohh = v hb ? v ho 0 . 2 5 0 . 3 0.45 v peak sink c u rr ent i ohh v ho = 0v 2 a peak sourc e c u rrent i olh v ho = 12v 2 a march 20 06 4 m9999-0315 06
mic r el, inc . mic41 00/1 pa r a me ter s y m b o l conditi o n m i n ty p ma x units s w itch ing specificatio n s lo w e r t u rn-o ff propagatio n dela y (li f a ll in g to lo f a lling ) t lph l (mic4100) 2 7 45 ns upper t u rn-o ff propagatio n dela y (hi f a ll i ng to ho f a llin g) t hp hl (mic4100) 2 7 45 ns lo w e r t u rn-o n propag atio n delay (li ris i ng to lo rising) t lplh (mic4100) 2 7 45 ns upper t u rn-o n propag atio n dela y (hi ris i n g to ho rising ) t hp l h (mic4100) 2 7 45 ns lo w e r t u rn-o ff propagatio n dela y (li f a ll in g to lo f a lling ) t lph l (MIC4101) 3 1 55 ns upper t u rn-o ff propagatio n dela y (hi f a ll i ng to ho f a llin g) t hp hl (MIC4101) 3 1 55 ns lo w e r t u rn-o n propag atio n delay (li ris i ng to lo rising) t lplh (MIC4101) 3 1 55 ns upper t u rn-o n propag atio n dela y (hi ris i n g to ho rising ) t hp l h (MIC4101) 3 1 55 ns delay m a tching: lo w e r t u rn-on and u pper t u rn-o ff t mo n 3 8 10 ns delay m a tching: lo w e r t u rn-off and u pper t u rn-o n t mo ff 3 8 10 ns either o u tput rise/f all t i me t rc , t fc c l = 1000pf 10 ns either o u tput rise/f all t i me (3v to 9v) t r , t f c l = 0 . 1 f 0 . 4 0 . 6 0.8 s minimum inp u t pulse w i dth that chan ges the o u tput t pw note 6 50 ns bootstrap di o de t u rn-o n or t u rn-of f t i me t bs 1 0 ns notes: 1. exceeding th e absolute maxi mum rating ma y damage the devi c e. 2. the device is not guarant eed t o function outside its operating ra ting. 3. devices are esd sensitive. ha ndling precautions recommended. human bod y mo del, 1.5k ? in series w i th 100p f. 4. specification f o r packaged pro duct onl y . 5. all voltages relative to pin7, v ss unless otherw i se specified 6. gua r anteed b y design. not p r o duction tested. march 20 06 5 m9999-0315 06
mic r el, inc . mic41 00/1 timing di agrams t hplh t lplh hi , l i ho , l o li hi lo ho t hplh t lplh t mon t moff note : a l l prop a g ati on dela y s ar e meas ured fr o m th e 50 % v o l t a g e le v e l. march 20 06 6 m9999-0315 06
mic r el, inc . mic41 00/1 ty pical characteri stics march 20 06 7 m9999-0315 06
mic r el, inc . mic41 00/1 ty pical characteri stics (cont.) march 20 06 8 m9999-0315 06
mic r el, inc . mic41 00/1 functi onal dia g ra m v dd hi li lo hs ho hb v ss driver uv l o uv l o le v e l shift driver hv figur e 1 . mic 4 1 0 0 func tion a l bloc k dia g r a m march 20 06 9 m9999-0315 06
mic r el, inc . mic41 00/1 functi onal de scri p tion the mi c41 0 0 is a hig h voltage, non-i n verting, dual mosfet dri v er that is desig ned to indep ende ntly drive both hig h -sid e and l o w-si de n-chan n e l mosfet s. the block dia g ra m of the mic4100 i s sh own in figure 1. both drivers contain an input buffer with hysteresi s , a uvlo ci rcuit and an out put buffer. the high -si de output buffer incl ud es a hig h sp eed level-shif ting circuit that is referen c ed to the hs pin. an internal di ode i s used a s p a rt of a b ootst ra p ci rcuit to p r ovide th e dri v e voltage fo r the high-sid e out put. startu p and uvlo the uvl o circuit force s the driver ou tput low until the sup p ly voltage excee d s th e uvlo thre shol d. the lo w-side uvlo circuit monitors the voltage bet wee n the vdd and vss pins. the high-side uvlo circuit m onitors the voltage betwe en the hb and hs pins. hy steresi s in the uvlo circuit p r eve n ts n o ise an d finite circui t impeda nce from cau s in g ch atter du ring turn -on. input stag e the mic4 10 0 and mic4 101 have dif f erent input stage s, whi c h let s these pa rts cover a wid e ra nge of drive r appli c ation s . both the hi a nd li pin s are refe ren c ed to the vss pin. the voltage state of the input signal does not cha nge the q u iesce n t current dra w of the driver. the mic41 0 0 has a high impedan ce, cmos comp atible input ran ge and is reco mmend ed for applicatio ns where the input si g nal is noi sy or where the input sig nal swi n g s the full ran g e of voltag e (fro m vd d to gnd ) . t h ere is typically 400 mv of hysteresi s on the in put pins thro ugho ut the vdd ran ge. th e hy stere s is imp r ov es noi se i m munity and p r event s input si gnal s with sl ow rise times from fa lsely trigge ring th e outp u t. t he th re shold voltage of the mic410 0 varies p r op orti onally with the vdd supply voltage. the amplitud e of the input signal affects the vdd supply curre n t. vin voltages th at are a di ode dro p le ss th an the vdd supply voltage will cause an increase in the vdd pi n curre n t. the grap h in figure 2 shows the t y pical depe nden ce betwe en i vdd and vin for vdd=12v. figure 2 the mic410 1 ha s a ttl com patible i nput rang e a nd i s recomme nde d for u s e with inputs sig nal s who s e am p litude is less than the supply voltage. the threshold le vel is indep ende nt of the vdd sup p ly voltag e and the r e is no depe nden ce betwe en i vdd and the inp u t signal am plitude with the MIC4101. thi s feat ure m a ke s the mic4 1 01 an excellent level translator t hat will drive high threshold mosfets fro m a low voltage pwm ic. lo w - side driv er a block dia g ram of the low-si de d r iver is sho w n in figure 3. the low-si de drive r is d e sig ned to drive a groun d (vss pin) refe re n c ed n-cha n nel mosf et. low driver impeda nces allow the ext e rnal m o sf et to be turned on and off qui ckl y . the rail-to-rail drive capability of the output ensure s a lo w rd so n fro m the externa l mosfet. a high level applied to li pi n cau s e s the uppe r drive r fet to turn o n a n d vdd voltag e is applie d t o the gate of the external m o sfet. a low level on th e li pin tu rn s off the uppe r d r iver and tu rn s o n the lo w side driver to g r ou nd the gate of the external mosf et. march 20 06 10 m9999-0315 06
mic r el, inc . mic41 00/1 march 20 06 11 m9999-0315 06 vs s vdd lo ex te rn a l fe t figure 3 high-side dr iv er and boo t str a p circ uit a block di ag ram of the high-sid e dri v er and bo o t strap circuit is sho w n in figu re 4. this drive r is de sign ed to drive a floating n-cha nnel m o sfet, who s e so urce te rminal is referen c ed to the hs pin. hs vdd ho e x t e r nal fe t hb c b figure 4 a low power, high sp eed, level shifting circuit isol ate s the low si de (vs s pin) refe re nce d circuit r y from the high-si de (hs pin) refe ren c ed d r iver. powe r to th e hig h -side d r iver and uv lo ci rcuit i s su ppli ed by the bo otstrap circuit while the voltage le vel of the hs pin is shifted high. the b ootst ra p ci rcuit con s ist s of an i n ternal dio d e and external capa citor, c b . in a typical appli c ation, su ch a s the synchro nou s buck conve r ter sho w n in f i gure 5, the hs pin is at gro und potential whil e the l o w-si d e mosfet i s o n . the internal diode all o ws capa citor c b to charg e up to vdd-vd du rin g this time (whe re vd is the forwa r d voltage drop of the internal di ode ). after the low-side m o sfet is turned off an d the ho pi n turn s on, t he voltage a c ro ss cap a cit o r c b is ap plied t o the gate of the up pe r externa l mosfet. as the uppe r m o sfet turn s on, voltage on the hs pin rises with the so urce of th e hig h - sid e mosfe t until it reache s vin. as the hs and hb pi n rise, the in ternal diode is reverse bia s ed preventing cap a cito r c b from discha rgin g. hs hb ho vd d c b lo lev e l sh if t hi li vs s vi n vo u t cout lo u t c vd d q1 q2 figure 5
mic r el, inc . mic41 00/1 march 20 06 12 m9999-0315 06 applicati on inf o rm ation po w e r dis s ipation consi d eratio ns powe r di ssi p a tion in the d r iver can be separated into three area s: ? internal dio d e dissi pation in the bootstrap circuit ? internal d r iver dissi pation ? quie scent cu rre nt dissip ation u s ed to supply the internal lo gic and control fu nction s. boo t str a p ci rcuit po w e r dissipa tion powe r di ssi p a tion of the i n ternal boot strap di ode pri m arily come s fro m the averag e cha r gin g curre n t of the c b cap a cito r tim e s the fo rwa r d voltage d r op of the d i ode. secon d a r y source s of di ode po we r dissipatio n a r e the reverse le akage current and reverse recovery effe cts of the diode. the avera g e current dra w n by repe ated cha r gi ng of the high-sid e mo sfet is cal c ulated by: frequency switching drive gate v at charge gate total q : where hb gate ) ( = = = s s gate ave f f f q i the ave r a ge power dissip ated by th e f o rward voltag e drop of the diode e qual s: drop voltage forward diode v : where f ) ( = = f ave f fwd v i pdiode t h e va lu e of v f shoul d be taken at the pea k current throug h the diode, ho we ver, this cu rrent is difficult to cal c ulate be cause of diffe ren c e s in so urce imp eda nce s . the pea k current ca n eith er be me asured or the val ue of v f at the average current can be used and will yield a good approximatio n of diode po wer di ssipatio n. the reverse l eakage cu rre nt of the internal boot stra p diode is typically 1 1ua at a re v e rse voltage of 100v and 125 c. powe r di ssip ation d ue to reverse le aka ge i s typically mu ch less than 1m w and can b e ignored. reverse re co very time is the time re qui red for th e inj e cted minority ca rri ers to be swept away from th e d e p l etion regio n d u ri ng turn -off of th e dio de. po wer dissipatio n due to reverse re covery can b e cal c ulated by computin g the averag e reve rse current d ue to reverse re cove ry charg e times the reverse voltage across the di ode. the ave r age reverse cu rrent and po wer di ssip a tion du e to revers e recovery can be estimate d by: time recovery reverse t current recovery reverse peak i : where 5 . 0 rr rrm ) ( ) ( = = = = rev ave rr rr s rr rrm ave rr v i pdiode f t i i the total diod e power di ssi pation is: rr fwd total pdiode pdiode pdiode + = an optional e x ternal boot strap dio de ma y be used in stead of the inte rna l diode (fi gure 6). an exte rnal diod e m a y be useful if hig h gate ch arge mosfets a r e being drive n and the po we r di ssipatio n of th e inte rnal di o de is contrib u t ing to exce ssive di e tempe r atu r es. th e volt age d r o p of the external dio d e must be le ss than the int e rnal diode f o r this option to work. the reverse voltage across the diod e will be e qual to the inp u t voltage mi nu s the vdd supply voltage. a 100v schottky diode will work for most 72vinput telecom ap pli c ation s . th e above equ ations can be u s ed to cal c ulate p o wer dissip ation in the extern al diode, ho wever, if the external diode h a s si gnifica n t reverse leaka g e curre n t, the powe r dissip ated in that dio de due to reverse leakage can be cal c ul ated as: supply power the of frequency switching fs / t cycle duty d voltage reverse diode v t and v at flow current reverse i : where ) 1 ( on rev j rev r = = = = = ? = s rev r rev f d v i pdiode the on -time i s the time th e high -si de switch i s cond ucting. in most po wer supply to pologi es, the diode i s re verse biased du ring the switching cycle off-tim e .
mic r el, inc . mic41 00/1 march 20 06 13 m9999-0315 06 hs hb ho vd d c b lo lev e l sh if t hi li vs s vi n ex t e r n a l diod e figure 6 gate d r iv er po w e r d i ssipation powe r di ssi p a tion in th e output d r iver stage i s mainly cau s e d by chargi ng a nd discha rgin g the gate to source and gate to drain cap a cit ance of the external mo sfet. figure 7 sh ows a simpl i fied equival ent ci rcuit o f the mic410 0 driv ing an extern al mosfet. hs hb ho ex t e rna l fet vd d c b rg r g_fe t ro n ro f f cg d cg s f i g u re 7 dissipa tion during the e x tern al m o sfet turn-on energy fro m cap a cito r c b is u s ed to ch arge up the i nput cap a cita nce of the mosf et (cg d and cgs). the e nergy delivere d to the m o sf et is di ssip a ted in the thre e resi stive co m pone nts, ro n , rg and rg _fet. ron is the on resi stan ce of the up per d r iv er m o sfe t in the mic4100. rg is the se ri es resi stor (if any) betwee n the driver i c and the mosfe t . rg_fet i s the g a te re sistan ce of the mosfet. rg _fet is usuall y listed in the powe r mosfet?s spe c ification s . the es r of cap a cito r c b and th e re sist ance of the co nne cting etch can be ig nored si nce they are much less than ron and rg _fet. the effe ctive cap a cita nce of cgd and cg s is difficult to cal c ulate sin c e th ey vary non -line a rly with id, vg s, an d vds. fortu n a tely, most power mos f et specifications inclu de a typical graph of tota l gate ch arge vs. vgs. figure 8 sho w s a typical g a te ch arge cu rve for an arbitra r y power mosfet. th is ch art sho w s that for a g a te voltage of 10v, the mosfet requi re s a bou t 23.5nc of charg e . the e nergy dissipate d by the re sistive comp one nts of the gate drive circuit du ring turn-on is cal c ulate d as: mosfet the of e capacitanc gate total the is ciss qg 1/2 e so v c q but 2 2 1 where v v ciss e gs gs = = = 10 8 6 4 2 0 0 5 10 15 20 25 gate char g e q g - t otal gate charge (nc ) v gs - gate-to-sourc e v oltage (v ) v ds = 50v i d = 6.9a figure 8 the same energy i s di ssi pated by roff, rg and rg_fet w h en the driver ic turns t he mosfet off. as s u ming r o n is approximat e ly equal to ro ff, the total energy and power dissipate d by the resi stive drive elem ent s is:
mic r el, inc . mic41 00/1 march 20 06 14 m9999-0315 06 the po we r di ssi pated i n sid e the mic4 10 0/1 is e qual t o the circuit drive gate the of frequency switching the is fs mosfet on the voltage source to gate the is vgs vgs at charge gate total the is qg off and on mosfet the switching by dissipated power the is p cycle switching per dissipated energy the is e qg qg e driver driver dirver where fs v p and v gs driver gs = = ratio of ron & roff to the external re si stive losse s in rg and rg_fet. letting ron =roff, t he power dissipated in the mic410 0 due to driving the external mo sfet is: fet rg rg ron ron p pdiss driver drive _ + + = supply current po w e r di ssipation s i p a t e d by the mic4100 due to sup p ly total po w e r dissipation a nd thermal consid era t ions s the di e tem peratu r e ma y be calcula t ed on ce th e total powe r is dissipate d in the mic410 0 even if is there i nothing bei n g driven. the suppl y cu rre n t is drawn b y th e bias fo r the i n ternal circuit r y, the level shifting circuitry and sho o t-throug h current i n the o u tput drivers. th e sup p ly curre n t is pro portion al to operatin g freq uen cy and th e vdd and vh b voltage s. the ty pical ch ara c t e risti c g r ap hs sho w how su pply curre n t varie s with switch ing fre que ncy and sup p ly voltage. the po wer d i s s cur r e n t is ihb vhb idd vdd pdiss ply + = sup total power dissipatio n in the mic410 0 or mic41 0 1 i equal to the po wer di ssi pation cau s e d by d r iving the external m o sfets, the sup p ly cu rre nt and the i n ternal bootstrap dio de. total drive ply total pdiode pdiss pdiss pdiss + + = sup power di ssi pa tion is kn own. ja total a j pdiss t t + = c/w) ( air ambient o junction t from resistance thermal the is mic4100/1 the of n dissipatio power the is pdiss c) ( emperature junction t the is t mperature ambient te maximum the is t : jc total j a where propaga tion dela y and dela y matchin g and oth e r timing cons ideration s propa gation delay a n d sig nal timi ng i s an i m porta nt t only to mi n i mize propa g a tion t i m e b e t ween the control e or a t i s l e s s t han the minim u m pulse wid t h may i m e r e q u i r e d for the c b e d f o r both th e lo w side (vdd) a nd hi gh side (hb) su pply pi ns. the s e capa citors e x t e r n a l con s id eratio n in a high p e rform a n c e power sup p l y . the mic410 0 i s desi gne d n o delay but to minimize the mi smat ch in delay betwe e n the high-sid e and low-side d r iv ers. fast pro pag a t ion del ay bet wee n the inp u t and outp u t drive waveform is desi r abl e. it improve s ove r cu rrent prot ection by decrea s in g the re spo n se sign al a n d the m o s f et gate drive. mi nimizin g prop agatio n delay al so minimizes p hase shift errors in power suppli e s with wide band width co ntrol loop s. many po we r su pply topologi es u s e two swit chin g mosfets o peratin g 18 0o out of pha se from ea ch other. these m o sf ets mu st n o t be on at th e s a m e t i m short ci rcuit will occur, causi ng hi gh peak current s and highe r po we r dissipatio n i n the mosf ets. the mic41 0 0 and mi c41 0 1 output gat e drive r s are not de sig n e d with anti-shoot -through prote c ti on ci rc uitry. the outp u t d r ives sign als simpl y follow the i nputs. t he p o we r supply desi g n must i n cl ude timing del ays (d ead -time) betwe en th e input sign als to prevent sho o t-thro ugh. the mic41 00 & mic410 1 d r iv ers spe c ify d e lay mat c hin g bet wee n th e two drivers to h e lp imp r ove power sup p ly perfo rma n ce by redu cin g the amount of dead -time re quire d betwe en the input sig nal s. care m u st b e taken to in sure th e in pu t sign al p u lse width is g r eate r th an the mini mum spe c ifi ed pul se wi dth. an input sign a l t h a result in no o u tput pul se or an output pu lse wh ose wi dth is signifi cantly less than the i nput. the maximu m duty cycle (ratio of hig h side on-ti me to swit chin g pe ri od) i s controll ed by the mi n i mum pul se width of the low side an d by t h e t cap a cito r to cha r ge du rin g the off-tim e . adequate time m u s t be a l low e d fo r the c b capa citor to ch arg e u p before the high-sid e driver i s turne d on. deco upling and boo t s t r a p cap acito r selection de cou p ling capa citors a r e req u i r sup p ly the cha r ge ne ce ssary to d r i v e t h e mosfets a s well as mi ni mize the volt age ri pple o n these pins. t he ca pacito r from hb to hs serves d oubl e d u ty by providin g de couplin g for th e high -si de circuit r y as we ll as providin g current to the hig h -si de circuit while the high -sid e external m o sfet is on. ce ra mic ca pacit ors a r e recomme nde d be ca use of their lo w im peda nce a n d sm all size. z5u t y pe ce rami c capa cito r diele c trics a r e n o t recomme nde d due to the l a rge chang e i n ca pa citan c e over temperature and voltag e. a minimum value of 0.1uf i s requi re d for each of the capa cito rs, rega rdl e ss o f the mosfets b e ing d r iven. larg e r m o sfets may requir e large r capa citance valu e s for prope r ope ration. t h e voltage ratin g of the cap a citors dep e nds on the sup p ly voltage, amb i ent tempera t ur e an d the voltage derating used for rel i ability. 25v rated x5r or x7r cerami c
mic r el, inc . mic41 00/1 march 20 06 15 m9999-0315 06 t h e bypass h e m o s f e t . cap a cito rs are re com m en ded fo r mo st appli c ation s . the minimum ca pacita n ce value sh ould b e increa sed if low voltage ca p a citors a r e use sin c e e v en good q uality dielectric capacitors, such as x 5 r, will l o se 40% to 70% of their ca pa cita nce valu e at the rated volta ge. placem ent o f the decou pling capa cit o rs i s criti c a l . the b y p a s s c a pac ito r for vd d s h ou ld be pla c ed as c l os e as possibl e bet wee n the v dd and v s s p i n s . cap a cit o r ( c b ) for th e hb sup p ly pin m u st be lo cate d as clo s e as po ssible bet wee n the hb and hs pin s . th e etch con n e c tion s must be sh ort, wide and direct. the u s e of a grou nd plan e to minimize co nne cti on imped an c e i s recomme nde d. refer to the sectio n on layout and comp one nt placem ent for more info rma t ion. the voltage on the boot strap capa cito r drop s ea ch t i me it delivers ch arge to turn on the mosfet. the voltag e dro p depe nd s on the gate cha r ge requi red b y t most mosfe t spe c ificatio ns spe c ify ga te cha r ge v s . vgs voltage. based on thi s in formation an d a re com m ende d ? v hb of less than 0.1v, the minimum value of bootstrap cap a cita nce is cal c ul ated a s : pin hb at the drop voltage ? v v at charge gate total q : where hb hb gate ' t hb gate b v q c the de cou p l i ng cap a cito r for the vdd input may be cal c ulate d in with th e sa me formula; ho wever, th e two cap a cito rs a r e usu a lly equ al in value. p e re p e a k currents r oun d t h e cu rre nt u s t also ke ep hb grounding, compon ent placemen t a nd circuit la y out nan o second swit chin g sp e eds and a m in and a r oun d the mi c41 00 an d mi c4 101 d r ivers require prop er pl ace m ent and trace r outing of all compo n e n t s . improp er pla c eme n t may cau s e de grad ed noise imm unity, false switching, excessive ringing o r ci rcuit latch-u p . f i g u r e 9 sh ow s th e cr itic al c u r r e n t pa ths w h en th e dr ive r outputs go hi gh a n d turn o n the extern al mosfet s. it also help s dem on strate th e ne ed for a lo w impeda n c e g plane. cha r g e need ed to turn-o n the mosfet g a tes come s fro m the decou pling capa cit o rs c vdd and c b . curre n t in the low-sid e gat e driver flo w s from c vdd through the intern al driver, into t he mosfet gate and o u t the source. t h e retu rn conn ection ba ck to the de co upling cap a cito r is made thro ugh the g r ound pl ane. a n y indu ctan ce or resi stan ce in the ground return path ca use s a voltage spi k e o r ri ngin g to appe ar o n the sou r ce of the mosfet. t h is voltag e works a gain s t the g a te drive voltage and can eithe r sl o w do wn o r tu rn off the mo sfet durin g the pe riod whe r e it sho u ld be turned on. curre n t in the high-sid e dri v er is sou r ce d from capa ci tor c b and flows int o the hb pin and out the ho pin, into the gate of the hi gh si de m o sfet. the retu rn p a t h f o r is from the source of the mosfet an d back to ca pacito r c b . the high-side circuit re turn path u s u a lly does n o t have a low imp eda nce g r o und p l ane so the e t ch conne ctio ns i n this critical p a th sho u ld b e sho r t and wide to mini mize parasitic inductance. a s wi th the low-s i de c i rc u i t , impeda nce betwe en the mosfet sou r ce and t h e decouplin g capa citor cau s e s ne gative voltage fee dba ck whi c h fights t he turn -on of the mosfet. it is imp o rta n t to note that ca pa citor cb must be pl ace d clo s e to th e hb an d hs pins. t h is cap a cito r n o t only provide s all the en ergy for turn -on but it m pin noi se an d rip p le lo w f o r p r op er op eration of the high - side d r ive ci rcuitry. hs hb ho vd d c b lo lev e l sh i f t hi li vs s lo c vdd gn d plan e gn d p l ane l o w - s i d e dr i v e t ur n- o n cu r r e nt pa th h i gh - s i d e d r i v e tu rn-o n c u rren t pa t h t u rn - o n c u r re n t pa t h s figure 9 figure 10 sh ows the critical cu t paths when the d r i v e r o lo w and tu r n e r n a l mosfets. short, w i m p eda n c e con n e c tio n s a r e im portant durin g turn -off rre n o f f t h e e x t outputs g l o for the same rea s on s giv en in the tu rn-on explan a t ion. curre n t flowi ng thro ugh t he internal diode repl eni she s cha r ge in the bootstrap cap a citor, cb.
mic r el, inc . mic41 00/1 march 20 06 16 m9999-0315 06 hs hb ho vd d c b lo lev e l sh i f t hi li vs s lo c vdd lo w - side d r iv e t u r n- o f f cu r r e nt pa th h i g h - s id e dr ive tu r n - o n c u rrent pa t h tur n -o ff c u rr e n t p a t h s figure 10 the follo wing circuit g u ide lines sh ould be ad he red t o fo r optimum ci rcuit perform an ce: 1. the vcc an d hb bypa ss ca pa citors must be placed clo s e to the sup p ly and g r ou n d pin s . it is critical th at th e etch l ength between the high side decouplin g capa citor (c b ) and th e hb & hs pi ns be minimi zed to redu ce lea d indu ctan ce. 2. a groun d plane should be used to minimize para s itic ind u c tan c e and i m peda nce of the return paths. th e m i c410 0 is ca pable of g r ea ter than 2a pea k current s a nd a n y i m peda nce b e twee n the mic410 0, the de cou p lin g ca pa citors and the external mosfet will degr ade the performance of the driver. 3. tra c e out the high di/dt an d dv/dt paths, as sh own in figure s 9 and 10 an d minimize etch length and loop area for these co nne ction s . minim i zing the s e para m eters decrea s e s t he pa ra sitic indu ctan ce and the radi ated emi ge nerate d by f a st ri se and fall times . a typical layout of a syn c hrono us bu ck conve r ter power stage (figu r e 11) is sho w n in figure 1 2 . hs hb ho vd d c b lo le v e l sh i f t hi li vs s vin c vd d hi gh- s i de f e t lo w- s i de f e t h s ( s wi t c h ) no d e ci n mic 4 1 0 0 figure 11
mic r el, inc . mic41 00/1 march 20 06 17 m9999-0315 06 the circuit i s co nfigured as a synchronou s bu ck power stage. the hi gh-side mos f et d r ain co nne cts to the input sup p ly voltage (d rain ) a nd t he source conn ect s to the swit chin g no de. the lo w-side m o sfet drain con n e cts to the swit chin g node a nd its sou r ce is co nne cted to ground. the bu ck co nverter outp u t i ndu ctor (not sh own) woul d con n e c t to the switchi ng n ode. th e hig h -si de d r ive t r ace, ho, i s route d on to p of i t s retu rn t r a c e, hs, to mi nimize loop are a a nd p a ra sitic indu ctan ce. the lo w-si de drive trace lo is routed ove r the gro und pl a ne whi c h mi n i mize s the imped an ce of that curre n t path. the de co u p ling cap a cit o rs, c b and c vdd are place d to minimize et ch l ength betwe en the cap a cito rs and thei r re spe c tive pin s . this clo s e pla c e m ent is ne ce ssary to efficiently cha r g e cap a cit o r c b when th e hs nod e is low. all traces a r e 0.025? wi de o r g r eate r to re duc e imp eda nce. cin i s used to decoupl e the high current path th rou g h the mosf ets. cb hs ho hb vdd hi li vss lo cvdd gnd (fet source ) mic4100 hs node (switching node) low-side fet v in (fet drain) high-side fet cin gnd ho trace figure 12
mic r el, inc . mic41 00/1 march 20 06 18 m9999-0315 06 package inform ation 8-pin soic (m ) micrel, inc. 2180 fortune drive san jose, ca 9513 1 usa t e l + 1 (408) 9 44-0 800 f a x + 1 (408) 47 4-1 000 w eb http:/ w w w . m i crel.co m the information f u rnished b y micrel in this data sh eet is belie ved to be accurate and reliable. ho w e ver, no responsibility is a ssumed by micr el for its use. micrel reserves the right to change circuitry a nd specifications at an y time w i tho u t notification to the customer. micrel products are not designed or autho ri zed for use as components in life support app liances, devices or sy stems where malfu nction of a product r e a s o n a b l y b e expected to res u lt in personal injury . life suppo rt devices or sy ste m s are devices or s y stems that (a ) are in tende d f o r s u r g i c a l i m p l a into the bod y or (b) support o r sustain life, and w h o s e failure to perf o rm can be re asonabl y e x pected to result in a significan t injury to th e user. a purchaser?s use or sale of micrel produc ts for use in life support app liances, devices or s y stems is a purchaser?s ow n risk and purchaser agre e s to full y indemnif y micrel for an y damages resulting from such use or sale. c a n n t ? 2004 micrel, in corporated.

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